Lead-Lag (LDLG)

This information applies to the
CompactLogix
5370,
ControlLogix
5570,
Compact GuardLogix
5370,
GuardLogix
5570,
Compact GuardLogix
5380,
CompactLogix
5380,
CompactLogix
5480,
ControlLogix
5580, and
GuardLogix
5580 controllers.
The Lead-Lag (LDLG) instruction provides a phase lead-lag compensation for an input signal. This instruction is typically used for feedforward PID control or for process simulations.
Available Languages
Ladder Diagram
This instruction is not available in ladder diagram.
Function Block
LDLG_FB_avail_v31
Structured Text
LDLG(LDLG_tag);
Operands
Function Block
Operand
Type
Format
Description
LDLG tag
LEAD_LAG
Structure
LDLG structure
Structured Text
Operand
Type
Format
Description
LDLG tag
LEAD_LAG
Structure
LDLG structure
See
Structured Text Syntax
for more information on the syntax of expressions within structured text.
LEAD_LAG Structure
Input Parameter
Data Type
Description
EnableIn
BOOL
Enable input. If cleared, the instruction does not execute and outputs are not updated.
Default is set.
In
REAL
The analog signal input to the instruction.
Valid = any float
Default = 0.0
Initialize
BOOL
Request to initialize filter control algorithm. When Initialize is set, Out = (In x Gain) + Bias.
Default = cleared
Lead
REAL
The lead time in seconds. Set Lead = 0.0 to disable the lead control algorithm. If Lead < 0.0, the instruction sets the appropriate bit in Status and limits Lead to 0.0. If Lead > maximum positive float, the instruction sets the appropriate bit in Status.
Valid = any float Greater than or equal to 0.0
Default = 0.0
Lag
REAL
The lag time in seconds. The minimum lag time is DeltaT/2. If Lag < DeltaT/2, the instruction sets the appropriate bit in Status and limits Lag to DeltaT/2. If Lag > maximum positive float, the instruction sets the appropriate bit in Status.
Valid = any float Greater than or equal to DeltaT/2
Default = 0.0
Gain
REAL
The process gain multiplier. This value allows the simulation of a process gain. The In signal is multiplied by this value. I = (In x Gain) + Bias
Valid = any float
Default = 1.0
Bias
REAL
The process offset level. This value allows the simulation of an ambient condition. This value is summed with the results of the multiplication of In times Gain. I = (In x Gain) + Bias
Valid = any float
Default = 0.0
TimingMode
DINT
Selects timing execution mode.
0 = Periodic rate
1 = Oversample mode
2 = Real-time sampling mode
Valid = 0 to 2
Default = 0
For more information about timing modes, see Function Block Attributes.
OversampleDT
REAL
Execution time for oversample mode.
Valid = 0 to 4194.303 seconds
Default = 0
RTSTime
DINT
Module update period for real time sampling mode
Valid = 1 to 32,767ms
Default = 1
RTSTimeStamp
DINT
Module time stamp value for real time sampling mode.
Valid = 0 to 32,767ms
Default = 0
Output Parameter
Data Type
Description
EnableOut
BOOL
Enable output.
Out
REAL
The calculated output of the algorithm. Math status flags are used for this output.
DeltaT
REAL
Elapsed time between updates. This is the elapsed time in seconds used by the control algorithm to calculate the process output.
Status
DINT
Status of the function block.
InstructFault (Status.0)
BOOL
The instruction detected one of the following execution errors. This is not a minor or major controller error. Check the remaining status bits to determine what occurred.
LeadInv (Status.1)
BOOL
Lead < minimum value or Lead > maximum value.
LagInv (Status.2)
BOOL
Lag < minimum value or Lag > maximum value.
TimingModeInv (Status.27)
BOOL
Invalid TimingMode value.
For more information about timing modes, see Function Block Attributes.
RTSMissed (Status.28)
BOOL
Only used in real time sampling mode. Set when
ABS | DeltaT - RTSTime | > 1 (.001 second).
RTSTimeInv (Status.29)
BOOL
Invalid RTSTime value.
RTSTimeStampInv (Status.30)
BOOL
Invalid RTSTimeStamp value.
DeltaTInv (Status.31)
BOOL
Invalid DeltaT value.
Description
The LDLG instruction supports one lead and lag in series. The instruction also allows configurable gain and bias factors. The LDLG instruction is designed to execute in a task where the scan rate remains constant.
The LDLG instruction uses this equation:
LDLG_fbd_eq
with these parameter limits:
Parameter
Limitations
Lead
LowLimit = 0.0
HighLimit = maximum positive float
Lag
LowLimit = DeltaT/2 (DeltaT is in seconds)
HighLimit = maximum positive float
Whenever the value computed for the output is invalid, NAN, or Plus or Minus sign INF, the instruction sets Out = the invalid value and sets the Math overflow status flag. When the value computed for the output becomes valid, the instruction initializes the internal parameters and sets Out = (In x Gain) + Bias.
Math Status Flags
No
Major/Minor Faults
None specific to this instruction. See
Common Attributes
for operand-related faults.
Execution
Function Block
Condition
Function Block Action
Prescan
EnableIn and EnableOut bits are cleared to false.
Tag.EnableIn is false
EnableIn and EnableOut bits are cleared to false.
Tag.EnableIn is true
EnableIn and EnableOut bits are set to true.
The instruction executes.
Instruction first run
N/A
Instruction first scan
Execute "Out = (In * Gain) + Bias".
Recalculate Lead/Lag coefficients.
Postscan
EnableIn and EnableOut bits are cleared to false.
Structured Text
Condition/State
Action Taken
Prescan
See Prescan in the Function Block table.
Normal Execution
See Tag.EnableIn is true in the Function Block table.
Postscan
See Postscan in the Function Block table.
Example
The LDLG instruction in this example adds a first-order lag to a simulated process. Optionally, you could enter a Gain on the LDLG instruction to simulate a process gain, and you could enter a Bias to simulate an ambient condition.
Function Block
LDLG_FB_ex_v31
Structured Text
DEDT_01.In := SimulatedLoop.CVEU;
DEDT(DEDT_01,DEDT_01_array);
LDLG_01.In := DEDT_01.Out;
LDLG(LDLG_01);
SimulatedLoop.PV := LDLG_01.Out;
PIDE(SimulatedLoop);
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