PBL rules for Set-reset gates

These rules apply for gates set to
Set-reset
 in Process Boolean Logic (PBL) instructions:
  • The dominant inputs (1 and 2) take precedence over the non-dominant (3 and 4) inputs.
  • If Input 1 is true and Input 2 is false, the output of the gate is set to true.
  • If Input 1 is false and Input 2 is true, the output of the gate is reset to false.
  • If Input 1 and Input 2 are true, the output of the gate is not changed.
  • If Input 1 and Input 2 are false, Inputs 3 and 4 determine the output:
    • If Input 3 is true and Input 4 is false, the output of the gate is set to true.
    • If Input 3 is false and Input 4 is true, the output of the gate is reset to false.
    • If both Input 3 and Input 4 are true, the output of the gate is not changed.
    • If both Input 3 and Input 4 are false, the output of the gate is not changed.
  • For a gate set to Set-Reset, configure at least one set input (either dominant or non-dominant) and one reset input (either dominant or non-dominant).
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