Scheduled Output Data

Scheduled Output Data

The output sent to the module has an additional schedule time (in CST time format). The output transition occurs when the module’s CST time matches the schedule time.
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The module ignores an unspecified number of high-order bits in the schedule time. Current modules ignore all of the high-order word and use part of the low-order word. It compares at least enough bits to schedule an event 16 seconds in the future.
The CST clock resides in the module and is synchronized with all the other clocks in the same chassis when there is a CST master in the chassis.
Input timestamping can be used in conjunction with the scheduled outputs feature so that, after input data changes state and a timestamp occurs, a synchronized output will actuate at some computed time in the future. You must allow a long enough delay so the timestamp gets input from the input module at its RPI, the control program computes the new output at its scan rate, and the output module gets its new data at its RPI. Generally, this will be several milliseconds.
The module keeps only one schedule time and overwrites it every time the controller sends new output. If you change the schedule time before the previously scheduled event, the previous event never happens. When the scheduled time occurs all outputs in the module switch to their new values. Before the scheduled time occurs, no outputs in the module change their states.
The most effective way to use the CST system to coordinate outputs with inputs is to use output and input modules residing in the same chassis and synchronized with the same CST master. This makes it possible to schedule an output change of state up to 16 seconds after an input change of state simply by doing arithmetic on the low order bits of the CST timestamps. The CST feature then performs the synchronization of outputs with inputs for you with a high degree of precision.
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