Program Conversion Error (PCE)

The Program Conversion Error (PCE) instruction is generated by the translation tool. The translation tool inserts a PCE instruction within the appropriate ladder rung to help you identify possible errors with a conversion.
When a file has finished importing, the bottom of the screen displays the results. Double-click on the errors in the results window to locate the PCE messages that the translation tool inserted. To complete the conversion process, you will want to locate, analyze, and fix any discrepancies using the PCE instructions.
An example of a PCE instruction follows:
*** Generated by Translation Tool: Source and destination types may differ *** ;
N: PCE(120, PCE011) COP(I1_008, N23[0], 4);
PCE Messages
Below is a list of all of the messages that are generated with a PCE instruction. The text is appended to the rung comments that have the PCE instruction. The message text begins with asterisks(*) and the words "Generated by Translation Tool", and ends with asterisks.
ID
Text
Accepted values
101
The address references a counter's Update Accum (UA) bit field. This is not supported in
Logix Designer
 software.
Each time a reference to a counter's UA field is encountered (
SLC
 only).
102
The address references a counter's Overflow(OV) or Underflow(UN) field. This has been translated but the translation needs to be validated.
Each time a reference to a counter's OV or UN field is encountered
103
Warning: Status files do not exist in
Logix Designer
 software. GSV instructions are used in
Logix Designer
 software to obtain controller information where applicable. This translation must be validated.
Each time a reference to the S file is encountered.
105
The address references an indirect file number. It was not translated.
Each time an address reference with an indirect file number is encountered.
107
The address reference may have an incorrect index. The translation needs to be validated.
Each time suitable index into the array could not be determined.
108
The BTR, BTW or MSG instruction has been translated. However, the translation needs to be validated. These instructions have many parameters that cannot be directly translated and require review.
Each time a BTR, BTW or MSG instruction is translated.
109
PLC-5
 and
SLC
s use 0.01 second and 1 second timebases.
Logix Designer
 software uses a 0.001 second time base. The address references ab Accumulator (ACC) field. The translation needs to be validated.
Each time a reference to a ACC field was encountered
110
PLC-5
 and
SLC
s use 0.01 second and 1 second timebases.
Logix Designer
 software uses a 0.001 second time base. The address references a Preset (PRE) field. The translation needs to be validated.
Each time a reference to a PRE field was encountered.
113
Follow the <FBC or DDT> instruction with MOV and FAL instruction on parallel branches to ensure the correct bits are being operated on.
Each FBC and DDT instruction.
114
Although the PID instruction has been translated, the PID instruction has many parameters that do not translate directly to
Logix Designer
 software. The translation must be verified.
Each time a PID instruction is translated.
115
16-bit parameters have been extended to 32-bit. Ensure bit manipulation is correct.
Each time BSL, BSR, BTD instruction is translated.
116
The structure of FOR/NXT/BRK statements has changed in the Logix architecture. In the
PLC-5
 processor, the FOR and NXT instruction enclosed a section of code that was to be iterated multiple times, while the BRK instruction allowed a way to break out of the repeating code. In the RSLogix architecture, the FOR instruction calls a given routine a specific number of times, so a NXT instruction is not needed. The BRK instruction works in a similar fashion as in the
PLC-5
 processor. Because this architecture change is significant, you will probably have to consider restructuring your logic.
Each time FOR/NXT/BRK instructions are encountered.
117
AGA instruction not supported.
Each time a AGA instruction is found.
119
CIR/COR not supported.
Each time a CIR or CIO instruction is found.
120
Source and destination types differ
When source and destination types differ in a COP instruction.
121
DFA instruction not supported
Each time a DFA instruction is found.
122
ERI/ERO instruction not supported.
Each time a ERI or ERO instruction is found.
123
IDI/IDO instruction not supported.
Each time a IDI or IDO instruction is found.
124
IIN/IOT instruction not supported.
Each time a IIN or IOT instruction is found.
128
SFC routines aren't translated.
Each time a SFR or EOT instruction is found.
129
Online edit instructions are not supported.
Each time a SDS, SIZ or SRZ instruction is found.
130
User Interrupt instructions not supported.
Each time a UID, UIE or UIF instruction is found.
131
DDV instruction not supported.
Each time a DDV instruction is found.
132
High Speed Counter instructions not supported.
Each time a HSC/HSD/HSE/ SL or RHC/RAC/TDF instruction is found.
133
I/O Interrupt Enable/Disable instructions not supported.
Each time a IID or IIE instruction is found.
134
IIM/IOM instruction not supported.
Each time a IIM or IOM instruction is found.
135
INT instruction not supported.
Each time a INT instruction is found.
136
REF instruction not supported.
Each time a REF instruction (in
SLC
) is found.
137
RPI instruction not supported.
Each time a RPI instruction is found.
138
Selectable Timed Interrupt instructions not supported.
Each time a STD/STE or STS instruction is found.
139
SUS instruction not supported.
Each time a SUS instruction is found.
141
RMP instruction not supported.
Each time a RMP instruction is found.
142
RPC instruction not supported.
Each time a RPC instruction is found.
143
SVC instruction not supported.
Each time a SVC instruction is found.
144
SWP instruction not supported.
Each time a SWP instruction is found.
145
SQC instruction not supported.
Each time a SQC instruction is found.
146
INV instruction not supported.
Each time a INV instruction is found.
147
DCD/ENC instruction not supported.
Each time a DCD or ENC instruction is found.
148
The CEM, DEM, or EEM instruction has been translated. However, the translation needs to be validated. These instructions have many parameters that cannot be directly translated and require review.
Each time a CEM, DEM or EEM instruction is found.
149
Modbus messaging is not supported in
Logix Designer
 software.
If MSG instruction is configured for Modbus.
150
MSG instruction and associated MESSAGE tag need to be manually verified.
Each time a MSG instruction is found.
151
Warning: Status files do not exist in
Logix Designer
 software. However this status file value is handled through the StatusFile routine.
S file type indexes that can be directly translated to functionality in
Logix Designer
 software.
152
Logix Designer
 software has a different fault handling mechanism then the
PLC-5
/
SLC
. This fault routine will not be called.
Start of identified legacy processor fault routine.
153
This PII/DII routine is not used by
Logix Designer
 software.
Start of identified legacy processor PII/DII routine.
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