Process Boolean Logic with Snapshot (PBL)

This information applies to the CompactLogix 5380P and ControlLogix 5580P controllers.
The Process Boolean Logic with Snapshot (PBL) instruction executes up to eight gates of configurable Boolean logic. Gate types available include AND, OR, XOR (Exclusive-OR), Set/Reset, Select, and Majority. Each gate provides up to four input conditions that are individually invertible using a configuration setting.
The PBL Instruction can record its current state:
  • After a change in output state.
  • On Operator or Program command.
  • Based on a logic loopback input.
Available Languages
Ladder Diagram
PAO_FeedbackAlarmConditions1
Function Block Diagram
PAO_FeedbackAlarmConditions1
Structured Text
PBL(PBL tag);
Operands
IMPORTANT:
Unexpected operation may occur if:
  • Output tag operands are overwritten.
  • Members of a structure operand are overwritten.
  • Except when specified, structure operands are shared by multiple instructions.
There are data conversion rules for mixing numeric data types within an instruction. See Data conversions.
Configuration Operands
Operand
Type
Format
Description
PBL
P_BOOLEAN_LOGIC
tag
Data structure required for proper operation of instruction.
P_BOOLEAN_LOGIC Structure
Public members are standard, visible tag members that are programmatically accessible. Private, hidden members are used in HMI faceplates and are not programmatically accessible. Private members are in separate tables after public members.
Public Input Members
Data Type
Description
EnableIn
BOOL
Enable input. Ladder Diagram: Corresponds to the rung condition.
Default is true.
Inp_InitializeReq
BOOL
1 = Request to initialize the instruction. The instruction is normally initialized in instruction first run. Use this request when reinitialization is needed. The instruction clears this operand automatically.
Default is true.
Inp_0
BOOL
Logic input 0.
Default is false.
Inp_1
BOOL
Logic input 1.
Default is false.
Inp_2
BOOL
Logic input 2.
Default is false.
Inp_3
BOOL
Logic input 3.
Default is false.
Inp_4
BOOL
Logic input 4.
Default is false.
Inp_5
BOOL
Logic input 5.
Default is false.
Inp_6
BOOL
Logic input 6.
Default is false.
Inp_7
BOOL
Logic input 7.
Default is false.
Inp_Hold
BOOL
1 = Hold previous states in snapshot; 0 = Pass live states to snapshot.
Default is false.
Inp_Reset
BOOL
1 = Reset snapshot latch, show live states.
Default is false.
Cfg_UseInpHold
BOOL
1 = Use Inp_Hold to snap state; 0 = Use Cmds or Output transition to snap.
Default is false.
Cfg_UsePCmd
BOOL
1 = Enable snapshot on PCmd_Snap 0 --> 1 (edge).
Default is true.
Cfg_UseOCmd
BOOL
1 = Enable snapshot on OCmd_Snap 0 --> 1 (edge).
Default is true.
Cfg_UseOut01
BOOL
1 = Enable snapshot on Output 0 --> 1 (rising edge).
Default is true.
Cfg_UseOut10
BOOL
1 = Enable snapshot on Output 1 --> 0 (falling edge).
Default is false.
Cfg_TimestampOnSnap
BOOL
1 = Generate a timestamp when snapshot occurs.
Default is false.
Cfg_SnapOver
BOOL
1 = New snapshot overwrites without reset, 0 = Save first snapshot until reset.
Default is false.
Cfg_HasMoreObj
BOOL
1 = Tells HMI an object with more information is available.
Default is false.
Cfg_HasNav
SINT
Set bits indicate which navigation buttons are enabled.
Default is 2#0000_0000.
Cfg_OnDly
REAL
Output ON delay time (seconds). Valid = 0.0 to 2147483.0
Default is 0.0.
Cfg_OffDly
REAL
Output OFF delay time (seconds). Valid = 0.0 to 2147483.0
Default is 0.0.
Cfg_CnfrmReqd
SINT
Operator Command Confirmation Required. Represents the type of command confirmation required. 0 = None, 1 = Command confirmation required, 2 = Performer e-signature required, 3 = Performer and approver e-signature required.
Default is 0.
PCmd_Snap
BOOL
Program command to capture Input, Gate states in snapshot.
Default is false.
PCmd_Reset
BOOL
Program command to reset (re-arm) snapshot latch.
Default is false.
Public Output Members
Data Type
Description
EnableOut
BOOL
Enable Output. This output state always reflects EnableIn input state.
Out_Live
BOOL
Condition logic output (result) after delay.
Out_Snap
BOOL
Condition logic output (result) at snapshot.
Val_DlyPctLive
DINT
Output OnDelay or OffDelay percent complete: live.
Val_DlyPctSnap
DINT
Output OnDelay or OffDelay percent complete: snapshot.
Val_SnapInit
DINT
Snapshot initiator: 1 = OCmd, 2 = PCmd, 3 = Out 0-->1, 4 = Out 1-->0, 5 = Inp_Hold.
Sts_Initialized
BOOL
1 = Instruction is initialized. Use Inp_InitializeReq to reinitialize.
Sts_Snapped
BOOL
1 = Snapshot has been triggered, 0 = Snapshot showing live states.
Sts_RdyReset
BOOL
1 = A latched alarm or shed condition is ready to be reset.
Sts_InpLive
SINT
Live input status bits: .0 to .7 = Inp_0 to Inp_7.
Sts_GateLive
SINT
Live gate result status bits: .0 to .7 = Gate 0 to 7.
Sts_InpSnap
SINT
Snapshot of input status bits: .0 to .7 = Inp_0 to Inp_7.
Sts_GateSnap
SINT
Snapshot of gate result status bits: .0 to .7 = Gate 0 to 7.
Sts_GateSrc1Live
SINT
Live wire state for source 1 of each gate (bit# = gate#).
Sts_GateSrc2Live
SINT
Live wire state for source 2 of each gate (bit# = gate#).
Sts_GateSrc3Live
SINT
Live wire state for source 3 of each gate (bit# = gate#).
Sts_GateSrc4Live
SINT
Live wire state for source 4 of each gate (bit# = gate#).
Sts_GateSrc1Snap
SINT
Snapshot of wire state for source 1 of each gate (bit# = gate#).
Sts_GateSrc2Snap
SINT
Snapshot of wire state for source 2 of each gate (bit# = gate#).
Sts_GateSrc3Snap
SINT
Snapshot of wire state for source 3 of each gate (bit# = gate#).
Sts_GateSrc4Snap
SINT
Snapshot of wire state for source 4 of each gate (bit# = gate#).
Sts_OutInvertLive
BOOL
Output after inverter but before TON/TOF timers.
Sts_OutInvertSnap
BOOL
Snapshot of output after inverter but before TON/TOF.
Sts_Err
BOOL
1 = Error in configuration: See detail bits (Sts_Errxxx) for reason.
Sts_ErrGateFunc
SINT
1 = Error in each gate's function code (use 0 to 6).
Sts_ErrGateSrcPtr
SINT
1 = Error in each gate's source pointer (use 0 to 15).
Sts_ErrGateSrcMask
SINT
1 = Error in each gate's mask (source used) configuration (qty, choice).
Sts_ErrOutSrcPtr
BOOL
1 = Error in output's source pointer (use 0 to 15).
Sts_ErrTimer
BOOL
1 = Error in output's On Delay or Off Delay preset (use 0.0 to 2147483.0).
Private Input Members
Data Type
Description
Cfg_GateFunc
DINT[8]
Function code for gate M (1 = AND, 2 = OR, 3 = XOR, 4 = 2oo3, 5 = Set-Reset).
Cfg_GateSrc1Invert
SINT
Gate M Source #1 is Inverted (M by bit) (1 = invert).
Default is 2#0000_0000.
Cfg_GateSrc1Mask
SINT
Gate M Source #1 is Used (M by bit) (1 = used).
Default is 2#0000_0000.
Cfg_GateSrc1Ptr
DINT[8]
Pointer to Gate M Source #1 (0...7 = inputs, 8...15 = gate outputs).
Cfg_GateSrc2Invert
SINT
Gate M Source #2 is Inverted (M by bit) (1 = invert).
Default is 2#0000_0000.
Cfg_GateSrc2Mask
SINT
Gate M Source #2 is Used (M by bit) (1 = used).
Default is 2#0000_0000.
Cfg_GateSrc2Ptr
DINT[8]
Pointer to Gate M Source #2 (0...7 = inputs, 8...15 = gate outputs).
Cfg_GateSrc3Invert
SINT
Gate M Source #3 is Inverted (M by bit) (1 = invert).
Default is 2#0000_0000.
Cfg_GateSrc3Mask
SINT
Gate M Source #3 is Used (M by bit) (1 = used).
Default is 2#0000_0000.
Cfg_GateSrc3Ptr
DINT[8]
Pointer to Gate M Source #3 (0...7 = inputs, 8...15 = gate outputs).
Cfg_GateSrc4Invert
SINT
Gate M Source #4 is Inverted (M by bit) (1 = invert).
Default is 2#0000_0000.
Cfg_GateSrc4Mask
SINT
Gate M Source #4 is Used (M by bit) (1 = used).
Default is 2#0000_0000.
Cfg_GateSrc4Ptr
DINT[8]
Pointer to Gate M Source #4 (0...7 = inputs, 8...15 = gate outputs).
Cfg_HasNav
SINT
Set bits indicate which navigation buttons are enabled.
Default is 2#0000_0000.
Cfg_OutSrcInvert
BOOL
Out source (before minimum duration timer) is inverted (1 = invert).
Default is false.
Cfg_OutSrcPtr
DINT
Source bit for Output (0...7 = inputs, 8...15 = gates).
Default is 0.
HMI_Const
SINT[9]
Constants (for use in HMI indirection of parameters).
OCmd_Reset
BOOL
Operator command to reset (re-arm) snapshot latch.
Default is false.
OCmd_Snap
BOOL
Operator Command to capture input, gate states in snapshot.
Default is false.
Private Output Members
Data Type
Description
ORdy_Reset
BOOL
1 = Ready for OCmd_Reset (enables button).
ORdy_Snap
BOOL
1 =Ready for OCmd_Snap (enables button).
Val_LastGate
DINT[8]
Last gate pin which uses this gate result (0 = not used, 1...32 = gates, 33 = output).
Val_LastInp
DINT[8]
Last gate pin which uses this input (0 = not used, 1...32 = gates, 33 = output) For animation.
Val_SnapTimestamp
DINT[7]
Snapshot timestamp [0] = year, [1] = month, [2] = day, [3] = hour, [4] = minute, [5] = second, [6] = usecond.
Operation
The PBL instruction:
  • Provides up to eight Boolean inputs and eight logic gates.
  • Each gate has four inputs. Each input can be enabled or disabled and can be normal or inverted. Each enabled gate input can be linked to a source, which is an instruction input or the result of a preceding gate
  • Use one of these methods to configure the eight gates:
    • Logical AND: The gate's output is true if all of the enabled gate inputs, after configured inversions, are true. An AND gate can have up to four inputs enabled.
    • Logical OR: The gate's output is true if any of the enabled gate inputs, after configured inversions, are true. An OR gate can have up to four inputs enabled.
    • Logical XOR (Exclusive OR): The gate's output is true if an odd number of the enabled gate inputs, after configured inversions, are true. An XOR gate can have up to four inputs enabled.
    • Set-Reset: The gate's output is set true if one of its Set inputs is true, and is cleared to false if one of its Reset inputs is true. The gate's four inputs are:
      Input 1: SET (dominant)
      Input 2: RESET (dominant)
      Input 3: SET
      Input 4: RESET
    • Select: If input 3 is false, the state of input 1 is passed to the gate output. If input 3 is true, the state of input 2 is passed to the gate output. A Select gate must have input 3 enabled and either or both of inputs 1 and 2 enabled.
    • Majority (labeled ‘MooN’ for ‘M out of N’): The gate’s output is set true if a majority of its inputs, after configured inversions, are true. A majority would consist of 2 out of 2, 2 out of 3, or 3 out of 4. A Majority gate can have two, three, or four inputs enabled.
  • Provides a snapshot capability that captures the state of the instruction for use later, until reset: all input states, gate states, and output state. The snapshot capability captures the state of the logic at the time that it tripped or shut down equipment, even if the logic states change after the shutdown. The snapshot is optionally timestamped from the controller clock with the year, month, day, hour, minute, second, or microsecond.
  • Provides options to enable these following snapshot trigger conditions:
    • Capture snapshot on Operator Command (OCmd_Snap).
    • Capture snapshot on Program Command (PCmd_Snap).
    • Capture snapshot when the output transitions from 0 to 1.
    • Capture snapshot when the output transitions from 1 to 0.
    • Capture snapshot of previous scan's state when a loopback input becomes true. This capability captures the snapshot when the PBL output condition is the first-out condition in a downstream PINTLK block. The first-out indication from the PINTLK instruction can be looped back to the PBL instruction's Inp_Hold input to hold the last-scan state in the snapshot, including last scan's time stamp.
Implementation
Use the PBL instruction in these situations:
  • A project requires an Interlock or Permissive condition that is more complicated than the simple OR-ing or AND-ing provided by the PINTLK (Interlocks) or PPERM (Permissives) Add-On Instructions.
  • A project requires some Boolean (combination) logic that can be reconfigured from the HMI online, or which requires the snapshot capability for saving a copy of the logic state with a timestamp.
  • A project contains more than the 16 interlock conditions or permissive conditions provided by the PINTLK and PPERM Add-On Instructions, but some of the conditions can be grouped together under one identification. For example, all of the bearing overtemperature signals for a pump and motor (Pump Inboard Bearing, Pump Outboard Bearing, Motor Inboard Bearing, and Motor Outboard Bearing) can be ORed together in a PBL instruction and the result presented to a PINTLK instruction as a single Bearing Overtemp condition.
Do not use this instruction in these situations:
  • A project requires simple interlocks and permissives that can be handled by the PINTLK and PPERM instructions directly. These instructions can permit operation or trip operation.
  • A project requires logic that is beyond the PBL Add-On Instruction capabilities or which is extremely time critical. The PBL instruction provides only eight inputs, eight gates, and one output with on-delay and off-delay timing, and it is implemented with table-driven code. Use hard-coded logic in native controller languages instead. The native programming languages are faster and provide functionality beyond what the PBL instruction can do.
This diagram illustrates the functionality of the PBL instruction:
PAO_FeedbackAlarmConditions1
Configuration
A maximum of eight gates can be configured using these tags:
Cfg_GateFunc[M] – This configuration is an array which defines the gate function. M = the gate number, 0-7.
  • 1 = Logical AND Gate
  • 2 = Logical OR Gate
  • 3 = Logical XOR Gate
  • 4 = Majority of Outputs are true
  • 5 = Set/Reset
  • 6 = A/B Selector
Each gate has four input pins. Each input pin can be enabled or disabled using this tag:
Cfg_GateSrc#Mask: This configuration is a SINT value that masks the gates (0-7) that are enabled for that input pin in a binary format. # = the input pin number (1-4). If the mask bit is high then the gate for that particular input pin is enabled.
Examples:
  • Cfg_GateSrc1Mask.0 = 1 input pin 1 of gate 0 is enabled
  • Cfg_GateSrc2Mask.1 = 1 input pin 2 of gate 1 is enabled
  • Cfg_GateSrc3Mask.3 = 1 input pin 3 of gate 3 is enabled
  • Cfg_GateSrc4Mask.0 = 1 input pin 4 of gate 0 is enabled
Each gate input pin can be normal or inverted.
Cfg_GateSrc#Invert: This configuration is a SINT value which inverts an input. # = the input pin number (1-4).
Examples:
  • Cfg_GateSrc1Invert.0 = 1 input pin 1 of gate 0 is inverted.
  • Cfg_GateSrc2Invert.2 = 1 input pin 2 of gate 2 is inverted
  • Cfg_GateSrc3Invert.3 = 1 input pin 3 of gate 3 is inverted
  • Cfg_GateSrc4Invert.6 = 1 input pin 4 of gate 6 is inverted
Each enabled gate input pin can be linked to a source, either an instruction input or the result of a preceding gate.
Cfg_GateSrc#Ptr[M] - This configuration is an array that defines the source for the input pin on each gate. Where # = the input pin number (1-4), and M = the gate number (0-7). A value of 0-7 represents an instruction input. A value of 8-15 represents the result of a preceding gate. Tip: A gate can only be used as an input into another gate with a higher gate value.
Examples:
  • Cfg_GateSrc1Ptr[0] = 2 states that Inp_2 is configured in Gate 0 on pin 1.
  • Cfg_GateSrc2Ptr[0] = 3 states that Inp_3 is configured in Gate 0 on pin 2.
  • Cfg_GateSrc3Ptr[2] = 8 states that Gate 0 result is configured in Gate 2 on pin 3.
  • Cfg_GateSrc4Ptr[7] = 12 states that Gate 4 result is configured in Gate 7 on pin 4.
Configure the output using these tags:
  • Cfg_OutSrcPtr – This configuration determines which input/gate will be the output. A value of 0-7 represents an instruction input. A value of 8-15 represents the result of a gate.
  • Cfg_OutSrcInvert – This configuration determines if the output will be inverted.
Configuration of Strings for HMI
Configure strings for HMI faceplates (FT View) and for the Logix Designer configuration dialog box. The strings are set to extended properties of tag items. Configure the strings in Logix Designer only.
  • Description
  • Label for graphic symbol
  • Display Library for HMI Faceplate call-up
  • Instruction name
  • Area name
  • URL link
  • State name strings for 0-state and 1-state
  • More Information
Monitor the PBL Instruction
Use the operator faceplate from the PlantPAx library of Process objects for monitoring.
Affects Math Status Flags
No.
Major/Minor Faults
None specific to this instruction. See Index Through Arrays for array-indexing faults.
Execution
Ladder Diagram
Condition/State
Action Taken
Prescan
Resets the output on-delay and off-delay timers; clears the snapshot time stamp and data; clears any commands received while controller was in Program mode.
Instruction first run
Resets the output on-delay and off-delay timers; clears the snapshot time stamp and data; clears any commands received while controller was in Program mode.
Rung-condition-in is false
Clears output to false (off) and resets the output on-delay and off-delay timers.
Rung-condition-in is true
Set rung-condition-out to rung-condition-in.
The instruction executes.
Postscan
Rung-condition-out is cleared to false.
Function Block Diagram
Condition/State
Action Taken
Prescan
Resets the output on-delay and off-delay timers; clears the snapshot time stamp and data; clears any commands received while controller was in Program mode.
Instruction first run
Resets the output on-delay and off-delay timers; clears the snapshot time stamp and data; clears any commands received while controller was in Program mode.
Instruction first scan
See instruction first run in the function block diagram table.
EnableIn is false
Clears output to false (off) and resets the output on-delay and off-delay timers.
EnableIn is true
EnableOut is set to true.
The instruction executes.
Postscan
EnableIn and EnableOut bits are cleared to false.
Structured Text
In Structured Text, EnableIn is always true during normal scan. The instruction executes when it is in the control path activated by the logic.
Condition/State
Action Taken
Prescan
See Prescan in the Function Block Diagram table.
Instruction first run
See Instruction first run in the Function Block Diagram table.
EnableIn is true
See EnableIn is true in the Function Block Diagram table.
Postscan
See Postscan in the Function Block Diagram table.
Example
This example uses the PBL instruction to perform advanced interlocking logic that is based on the winding temperatures of a motor. This example navigates the parameter settings to fully illustrate the example.
In this example, there is a motor with three RTDs measuring temperature of the windings. To prevent damage to the windings, the motor must be interlocked if:
  • Any of the windings are above the high-high temperature limit.
  • The majority of the windings are above the high temperature limit.
PBL performs this function. The output of this logic feeds the interlock of the motor elsewhere in logic.
Ladder Diagram
PAO_FeedbackAlarmConditions1
Function Block Diagram
PAO_FeedbackAlarmConditions1
In this example, there is a motor with three RTDs measuring temperature of the windings. To prevent damage to the windings, the motor must be interlocked if any of the three windings are above the high-high temperature limit, or if the majority of the windings are above the high temperature limit. PBL is being used to perform this function. The output of this logic feeds the interlock of the motor elsewhere in logic.
The input parameters (Inp_0, Inp_1, Inp_2, Inp_3, Inp_4, Inp_5) are connected to the status outputs of the three winding temperature inputs. Three of the eight gates (0…7) in PBL are used in this example (1, 5, 6). Gate 1 is the OR of the three high-high status bits. Gate 5 checks if the majority of the high status bits are true. Gate 6 ORs the outputs of Gates 1 and 5 to set the output of PBL.
To set up the gate functions (Gates 1 and 6 as OR and Gate 5 as Majority), use these settings:
  • Cfg_GateFunc[1] = 2
  • Cfg_GateFunc[5] = 6
  • Cfg_GateFunc[6] = 2
Gate 1 is set up to look at the three high-high status inputs (Inp_0, Inp_2, and Inp_4) by using these settings:
  • Cfg_GateSrc1Mask.1 = 1, Cfg_GateSrc1Ptr[1] = 0
  • Cfg_GateSrc2Mask.1 = 1, Cfg_GateSrc2Ptr[1] = 2
  • Cfg_GateSrc3Mask.1 = 1, Cfg_GateSrc3Ptr[1] = 4
Gate 5 is set up to look at the three high status inputs (Inp_1, Inp_4, and Inp_5) by using these settings:
  • Cfg_GateSrc1Mask.5 = 1, Cfg_GateSrc1Ptr[5] = 1
  • Cfg_GateSrc2Mask.5 = 1, Cfg_GateSrc2Ptr[5] = 3
  • Cfg_GateSrc3Mask.5 = 1, Cfg_GateSrc3Ptr[5] = 5
Lastly, Gate 6 is set up to look at the outputs of gates 1 and 5 by using these settings:
  • Cfg_GateSrc1Mask.6 = 1, Cfg_GateSrc1Ptr[6] = 9
  • Cfg_GateSrc2Mask.6 = 1, Cfg_GateSrc2Ptr[6] = 13
Cfg_OutSrcPtr needs to be set to 14 to take the output from Gate 6 and make it the output (Out_Live) of the PBL block. The on-delay time is then set to 5 seconds to prevent spurious trips of the output (Cfg_OnDly = 5).
Lastly, the descriptions provide documentation on the faceplate. In this example, these are the description settings:
  • Out_Live.@State0 = OK
  • Out_Live.@State1 = Tripped
  • Inp_0.@Label = Winding A Hi-Hi Temp
  • Inp_1.@Label = Winding A Hi Temp
  • Inp_2.@Label = Winding B Hi-Hi Temp
  • Inp_3.@Label = Winding B Hi Temp
  • Inp_4.@Label = Winding C Hi-Hi Temp
  • Inp_5.@Label = Winding C Hi Temp
This diagram illustrates the functionality of the example:
PAO_FeedbackAlarmConditions1
Structured Text
TI1_P50.Inp_PVData := I_TE1_P50;
TI1_P50.Inp_PVUncertain := (CAF_117[12] OR Local_12_I_CH0Fault);
PAI(TI1_P50);
TI2_P50.Inp_PVData := I_TE2_P50;
TI2_P50.Inp_PVUncertain := (CAF_117[12] OR Local_12_I_CH1Fault);
PAI(TI2_P50);
TI3_P50.Inp_PVData := I_TE3_P50;
TI3_P50.Inp_PVUncertain := (CAF_117[12] OR Local_12_I_CH2Fault);
PAI(TI3_P50);
TI1_P50.Sts_HiHi := NG_PBL.Inp_0;
TI1_P50.Sts_Hi := NG_PBL.Inp_1;
TI2_P50.Sts_HiHi := NG_PBL.Inp_2;
TI2_P50.Sts_Hi := NG_PBL.Inp_3;
TI3_P50.Sts_HiHi := NG_PBL.Inp_4;
TI3_P50.Sts_Hi := NG_PBL.Inp_5;
PBL(NG_PBL);
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